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DS8007A multiprotocol dual smart card interface ________________________________________________________________ maxim integrated products 1 rev 0; 4/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of a ny device may be simultaneously available through various sales channels. for information about device errata, go to: www.maxim-ic.com/errata . evaluation kit available general description the DS8007A multiprotocol dual smart card interface is an automotive grade, low-cost, dual smart card reader interface supporting all iso 7816, emv, and gsm11- 11 requirements. through its 8-bit parallel bus and dedi- cated address selects (ad3?d0), the DS8007A can easily and directly connect to the nonmultiplexed byte- wide bus of a maxim secure microcontroller. optionally, the parallel bus can be multiplexed to allow direct access to the multiplexed bus of an 80c51-compatible microcontroller through movx memory addressing. one integrated uart is multiplexed among the inter- faces to allow high-speed automatic smart card pro- cessing with each card-possessing, independent, variable, baud-rate capability. the card interface is con- trolled by internal sequencers that support automatic activation and deactivation sequencing, handling all actions required for t = 0, t = 1, and synchronous pro- tocols. emergency deactivation is also supported in case of supply dropout. a third card is supported through the auxiliary i/o. the same set of i/o can option- ally be used as additional serial interface for the uart. the DS8007A provides all electrical signals necessary to interface with two smart cards. the integrated volt- age converter ensures full cross-compatibility between 1.8v/3v/5v cards and a 1.8v/3v/5v environment, and allows operation within a 2.7v to 6v supply voltage range. the standard ds8007 revision is available for nonautomotive applications. applications banking applications (point-of-sale terminals, debit/credit payment terminals, pin pads, automated teller machines) telecommunications pay television access control features ? complete interface/control for two separate smart card devices ? 8kv (min) esd protection on card interfaces ? internal ic card supply voltage generation 5.0v ?%, 65ma (max) 3.0v ?%, 50ma (max) 1.8v ?0%, 30ma (max) ? automatic card activation, deactivation, and data communication controlled by dedicated internal sequencer ? host interface through an 8-bit parallel bus (user- selectable multiplexed or nonmultiplexed modes) ? chip select and three-state bus allow multiple devices (card readers and memories) on bus ? 8-character receive fifo with optional programmable depth/threshold ? i/o interface pin to external iso 7816 uart ? separate card clock generation (up to 10mhz) with 2x frequency doubling ? selectable card clock stop high, stop low, or internally generated 1.25mhz (for card power-down) ? emv-certified reference design and evaluation kit available (ds8007-kit) ordering information typical operating circuit appears at end of data sheet. part temp range smart cards supported pin- package DS8007A-eag+ -40c to +125c 2 + auxiliary 48 lqfp + denotes a lead(pb)-free/rohs-compliant device. emv is a trademark owned by emvco llc. rd d7 d6 d5 d4 d3 d2 d1 d0 v dd cpa2 agnd rstout i/oaux i/oa c8a presa c4a gnda clka v cca rsta i/ob c8b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 presb c4b gndb clkb v ccb rstb gnd v up cpa1 cpb1 v dda cpb2 delay xtal1 xtal2 ad0 ad1 ad2 ad3 intaux int ale cs wr lqfp DS8007A + pin configuration
DS8007A multiprotocol dual smart card interface 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +3.3v, v dda = +3.3v, t a = +25?, unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v dd relative to ground ...........-0.5v to +6.5v voltage range on v dda relative to ground .........-0.5v to +6.5v voltage range on any pin relative to ground pins cpa1, cpa2, cpb1, cpb2, and v up .........-0.5v to +7.5v all other pins...........................................-0.5v to (v dd + 0.5v) maximum junction temperature .....................................+150? maximum power dissipation (t a = -25?) .......................900mw storage temperature range .............................-55? to +150? soldering temperature...........................refer to the ipc/jedec j-std-020 specification. parameter symbol conditions min typ max units digital supply voltage v dd 2.7 6.0 v step-up converter supply voltage v dda v dd 6.0 v cards inactive f xtal = 0mhz 0.9 power-down v dd current cards active i pd f xtal = 0mhz, f clk = 0mhz, v ccx = 5v 2.2 ma sleep mode v dd current (cards active) i stop f clk = 0mhz, v cc = 5v 24 ma active v dd current 5v cards i dd 3x v dd step-up: i cca + i ccb = 80ma, v dd = 2.7v, f xtal = 20mhz, f clk = 10mhz 325 ma 2x v dd step-up: i cc1 + i cc2 = 80ma, f xtal = 20mhz, f clk = 10mhz, v dd = 2.7v 225 active v dd current 3v cards i dd no step-up: i cc1 + i cc2 = 80ma, f xtal = 20mhz, f clk = 10mhz, v dd = 5v 120 ma v rst threshold voltage (falling) 2.1 2.5 v power-fail reset voltage v hys hysteresis 50 170 mv reset threshold v drst 1.25 output voltage v do v dd + 0.3 v v delay = 0v -2 a output current i do v delay = v dd +2 ma delay pin output capacitance c do 1 nf rstout pin output high voltage v ohrsto i oh = -1ma 0.8 x v dd v dd + 0.3 v output low voltage v olrsto i ol = 2ma -0.3 +0.4 v leakage current i l v ol = 0v, v oh = 5v -10 +10 a
DS8007A multiprotocol dual smart card interface _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +3.3v, v dda = +3.3v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units alarm pulse width t w c delay = 22nf 10 ms external crystal 4 20 external clock frequency f xtal external oscillator 0 20 mhz internal oscillator f int 1.6 2.5 3.7 mhz 3x step-up 5.7 voltage on v up pin v up 2x step-up 4.1 v voltage detection of v dda for 2x, 3x step-up v det 3.25 3.50 3.60 v shutdown temperature t sd +150 c output low voltage v olrst i olrst = 1ma 0 0.3 v card inactive mode output current i olrst v olrst = 0v 0 -1 ma output low voltage v olrstl i olrst = +200a 0 0.3 output high voltage v ohrsth i ohrst = -200a v cc C 0.5 v cc v rise time t rrst c l = 30pf 0.1 fall time t frst c l = 30pf 0.1 s shutdown current i rst(sd) -25 rstx pins card active mode current limitation i rst(limit) -30 +30 ma output low voltage v olclk i olclk = 1ma 0 0.3 v card inactive mode output current i olclk v olclk = 0v 0 -1 ma output low voltage v olclk i olclk = +200a 0 0.3 output high voltage v ohclk i ohclk = -200a v cc C 0.5 v cc v rise time t rclk c l = 30pf (note 2) 8 fall time t fclk c l = 30pf (note 2) 8 ns card active mode current limitation i clk(limit) -90 +90 ma idle configuration (1mhz) 1 1.85 clkx pins clock frequency f clk operational 0 10 mhz duty factor c l = 30pf 45 55 %
DS8007A multiprotocol dual smart card interface 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = +3.3v, v dda = +3.3v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units output low voltage v cc i cc = 1ma 0 0.3 v card inactive mode output current i cc v cc = 0v 0 -1 ma i cc(5v) < 65ma 4.72 5.00 5.25 i cc(3v) < 50ma 2.75 3.00 3.22 i cc(1.8v) < 30ma 1.62 1.80 1.95 5v card, current pulses of 40nc with i < 200ma, t < 400ns, f < 20mhz 4.6 5.4 3v card, current pulses of 24nc with i < 200ma, t < 400ns, f < 20mhz 2.75 3.25 output low voltage v cc 1.8v card, current pulses of 12nc with i < 200ma, t < 400ns, f < 20mhz 1.62 1.98 v v cc(5v) = 0 to 5v -65 v cc(3v) = 0 to 3v -50 output current i cc v cc(1.8v) = 0 to 1.8v -30 total current (two cards) i cc(a+b) -80 shutdown current i cc(sd) -100 ma v ccx pins card active mode slew rate v ccsr up/down, c < 300nf (note 3) 0.05 0.16 0.5 v/s output low voltage v olio i olio = 1ma 0 0.3 v output current i olio v olio = 0v 0 -1 ma card inactive mode internal pullup resistor r pullup to v ccx 9 14 19 k output low voltage v olio i olio = 1ma 0 0.3 i ohio -20a 0.8 x v cc v cc output high voltage v ohio i ohio -40a (3v/5v) 0.75 x v cc v cc v output rise/fall time t ot c l = 30pf 0.1 s input low voltage v ilio -0.3 +0.8 input high voltage v ihio 1.5 v cc v input low current i ilio v ilio = 0v 700 input high current i ihio v ihio = v cc 20 a input rise/fall time t it c l = 30pf 1.2 s i/ox pins card active mode current limitation i io(limit) -25 +25 ma
DS8007A multiprotocol dual smart card interface _______________________________________________________________________________________ 5 electrical characteristics (continued) (v dd = +3.3v, v dda = +3.3v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units output low voltage v olc48 i olc48 = 1ma 0 0.3 v output current i olc48 v olc48 = 0v 0 -1 ma card inactive mode internal pullup resistor r pullup between c4 or c8 and v ccx 6 10 14 k output low voltage v olc48 i olc48 = 1ma 0 0.35 i ohc48 -20a 0.8 x v cc v cc output high voltage v ohc48 i ohc48 -40a (3v/5v) 0.75 x v cc v cc v output rise/fall time t ot c l = 30pf 0.1 s input low voltage v ilc48 -0.3 +0.8 input high voltage v ihc48 1.5 v cc v input low current i ilc48 v ilio = 0v 850 input high current i ihc48 v ihio = v cc 20 a input rise/fall time t it c l = 30pf 1.2 s pullup pulse width t wpu active pullup 200 ns c4x, c8x pins card active mode operating frequency f max on card contact pins 1 mhz timing activation sequence duration t act see figure 9 130 s deactivation sequence duration t de see figure 9 150 s presa/presb pins input low voltage v ilpres 0.25 x v dd v input high voltage v ihpres 0.7 x v dd v input low current i ilpres v ilpres = 0v 40 a input high current i ihpres v ihpres = v dd 40 a i/oaux pin internal pullup resistor r pullup between i/oaux and v dd 9 14 19 k output low voltage v olaux i olaux = 1ma 0.3 v output high voltage v ohaux i ohaux = 40a (3v/5v) 0.75 x v dd v dd v output rise/fall time t ot c l = 30pf 0.1 s
DS8007A multiprotocol dual smart card interface 6 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = +3.3v, v dda = +3.3v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units input low voltage v ilaux -0.3 0.3 x v dd v input high voltage v ihaux 0.7 x v dd v dd v input low current i ilaux v ilaux = 0v 700 a input high current i ihaux v ihio = v dd -20 +20 a input rise/fall time t it c l = 30pf 1.2 s interrupt pin output low voltage v olint i oh = 2ma 0.3 v input high leakage current i lihint 10 a d7 to d0, all other logic pins output low voltage v old i old = +5ma 0.2 x v dd v output high voltage v od i ohd = -5ma 0.8 x v dd v dd v output rise/fall time t ot c l = 50pf 25 ns input low voltage v ild 0.3 x v dd v input high voltage v ihd 0.7 x v dd v input low current i ild -20 +20 a input high current i ihd -20 +20 a load capacitance c ld 10 pf note 1: operation guaranteed at -40? but not tested. note 2: parameters are guaranteed to meet all iso 7816, gsm11-11, and emv 2000 requirements. for the 1.8v card, the maxi- mum rise and fall time is 10ns. note 3: parameter is guaranteed to meet all iso 7816, gsm11-11, and emv 2000 requirements. for the 1.8v card, the minimum slew rate is 0.05v/? and the maximum slew rate is 0.5v/?.
DS8007A multiprotocol dual smart card interface _______________________________________________________________________________________ 7 ac electrical specifications?iming parameters for multiplexed parallel bus (v dd = 3.3v, v dda = 3.3v, t a = +25?, unless otherwise noted.) (figure 1) parameter symbol conditions min typ max units xtal 1 cycle time t cy(xtal1) 50 ns ale pulse width t w(ale) 20 ns address valid to ale low t avll 10 ns ale low to rd or wr low t (al-rwl) 10 ns register urr 2 x t cy(xtal1) rd pulse width t w(rd) other registers 10 ns rd low to data read valid t (rl-dv) 50 ns wr / rd high to ale high t (rwh-ah) 10 ns wr pulse width t w(wr) 10 ns data write valid to wr low t (dv-wl) 10 ns ale cs d7?0 rd wr address address data (read) data (write) t w(ale) t avll t (al-rwl) t w(rd) t (rl-dv) t (rwh-ah) t (dv-wl) t (rwh-ah) t w(wr) figure 1. multiplexed parallel bus timing
DS8007A multiprotocol dual smart card interface 8 _______________________________________________________________________________________ t 4 data in address write release with cs write release with en t 6 t 7 t 1 t 8 data out address cs read write wr (en) rd (r/w) ad3?d0 d7?0 cs wr (en) cs wr (en) rd (r/w) ad3?d0 d7?0 t 2 t 3 t 5 figure 2. nonmultiplexed parallel bus timing (read and write) ac electrical specifications?iming parameters for nonmultiplexed parallel bus (read and write) (v dd = 3.3v, v dda = 3.3v, t a = +25?, unless otherwise noted.) (see figure 2.) parameter symbol conditions min typ max units rd high to cs low t 1 10 ns access time cs low to data out valid t 2 50 ns cs high to data out high impedance t 3 10 ns data valid to end of write t 4 10 ns data hold time t 5 10 ns rd low to cs or wr low t 6 10 ns address stable to cs or wr high t 7 10 ns address to cs low t 8 10 ns
DS8007A multiprotocol dual smart card interface _______________________________________________________________________________________ 9 ac electrical specifications?iming parameters for consecutive read/write to urr/utr/toc (v dd = 3.3v, v dda = 3.3v, t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units see figure 3 rd pulse width t w(rd) 10 ns rd low to bit cred = 1 t rd(urr) t w(rd) + 2t cy(clk) t w(rd) + 3t cy(clk) ns set time bit fe t sb(fe) 10.5 etu set time bit rbf t sb(rbf) 10.5 etu see figure 4 wr / cs pulse width t w(wr) (note 4) 10 ns wr / cs low to i/o low t wr(utr) t w(wr) + 2t cy(clk) t w(wr) + 3t cy(clk) ns see figure 5 wr / cs pulse width t w(wr) 10 ns wr / cs high to bit cred = 1 t w(toc) (notes 4 and 5) 1 / psc 2 / psc etu t sb(rbf) t w(rd) t sb(fe) i/ox rbf bit fe bit int rd cred bit t rd(urr) figure 3. timing between two read operations in register urr note 4: depends on the leading edge of wr or cs (whichever is deasserted first). reference this specification to the rising edge of cs / wr instead of the falling edge. note 5: psc is the programmed prescaler value (31 or 32).
DS8007A multiprotocol dual smart card interface 10 ______________________________________________________________________________________ t w(wr) t wr(utr) i/ox tbe bit wr/cs cred bit int figure 4. timing between two write operations in register utr t wr(toc) t w(wr) wr/cs cred bit figure 5. timing between two write operations in register toc
DS8007A multiprotocol dual smart card interface ______________________________________________________________________________________ 11 pin description pin name function 1 rstout reset output. this active-high output is provided for resetting external devices. the rstout pin is driven high until the delay pin reaches v drst . once the delay pin reaches v drst , the rstout pin is tri-stated so it can externally be pulled down. the supl bit is set for each rstout pulse. 2 i/oaux auxiliary i/o. this i/o pin allows connection to an auxiliary smart card interface. 3 i/oa smart card a i/o data line. this is the i/o data line associated with smart card a. this is also referred to as the iso c7 contact. 4 c8a smart card a auxiliary i/o. this is an auxiliary i/o associated with smart card a. this is also referred to as the iso c8 contact. this can be associated with synchronous cards. 5 presa smart card a presence contact. this is the active-high presence contact associated with smart card a. 6 c4a smart card a auxiliary i/o. this is an auxiliary i/o associated with smart card a. this is also referred to as the iso c4 contact. this can be associated with synchronous cards. 7 gnda smart card a ground. this must be connected to gnd. 8 clka smart card a clock output. this is the clock output associated with smart card a. this is also referred to as the iso c3 contact. 9 v cca smart card a supply voltage. this is the supply voltage output associated with smart card a. this is also referred to as the iso c1 contact. 10 rsta smart card a reset. this is the reset output associated with smart card a. this is also referred to as the iso c2 contact. 11 i/ob smart card b i/o data line. this is the i/o data line associated with smart card b. this is also referred to as the iso c7 contact. 12 c8b smart card b auxiliary i/o. this is an auxiliary i/o associated with smart card b. this is also referred to as the iso c8 contact. this can be associated with synchronous cards. 13 presb smart card b presence contact. this is the active-high presence contact associated with smart card b. 14 c4b smart card b auxiliary i/o. this is an auxiliary i/o associated with smart card b. this is also referred to as the iso c4 contact. this can be associated with synchronous cards. 15 gndb smart card b ground. this must be connected to gnd. 16 clkb smart card b clock output. this is the clock output associated with smart card b. this is also referred to as the iso c3 contact. 17 v ccb smart card b supply voltage. this is the supply voltage output associated with smart card b. this is also referred to as the iso c1 contact. 18 rstb smart card b reset. this is the reset output associated with smart card b. this is also referred to as the iso c2 contact. 19 gnd ground 20 v up step-up converter connection. connect a low-esr capacitor of 220nf between this pin and ground.
DS8007A multiprotocol dual smart card interface 12 ______________________________________________________________________________________ pin description (continued) pin name function 21 cpa1 step-up converter contact 1. connect a low-esr capacitor of 220nf between cpa1 and cpa2. 22 cpb1 step-up converter contact 3. connect a low-esr capacitor of 220nf between cpb1 and cpb2. 23 v dda analog supply voltage. positive analog-supply voltage for the step-up converter; can be higher but not lower than v dd. this pin should be decoupled to agnd with a good quality capacitor. 24 cpb2 step-up converter contact 4. connect a low-esr capacitor of 220nf between cpb1 and cpb2. 25 agnd analog ground 26 cpa2 step-up converter contact 2. connect a low-esr capacitor of 220nf between cpa1 and cpa2. 27 v dd digital supply voltage. this pin should be decoupled to gnd with a good quality capacitor. 28C35 d0Cd7 8-bit digital i/o. this port functions as the data or address/data communication lines between the host controller and the DS8007A for the nonmultiplexed and multiplexed operating modes, respectively. 36 rd active-low parallel bus read strobe input. in multiplexed mode, this input indicates when the host processor is reading information from the DS8007A. in nonmultiplexed mode, this pin signals the current operation is a read ( rd = 1) or a write ( rd = 0) when cs and wr are low. 37 wr active-low parallel bus write strobe input. in multiplexed mode, this input indicates when the host processor is writing information to the DS8007A. in nonmultiplexed mode, a low on this pin signals the bus is engaged in a read or write operation. 38 cs active-low chip-select input. this input indicates when the DS8007A is active on the parallel bus. 39 ale address latch enable input. this signal monitors the ale signal when the host processor bus is operating in multiplexed mode. connect this signal to v dd when operating in nonmultiplexed mode. 40 int active-low interrupt. this output indicates an interrupt is active. 41 intaux auxiliary interrupt input. this pin serves as an auxiliary interrupt. 42C45 ad3Cad0 register selection address inputs. these pins function as the address input lines for the nonmultiplexed configuration and should be connected to ground or v dd in the multiplexed configuration. 46, 47 xtal2, xtal1 crystal oscillators. place a crystal with appropriate load capacitors between these pins if that is the desired clock source. xtal1 also acts as an input if there is an external clock source in place of a crystal. 48 delay external delay capacitor connection. connect a capacitor from this pin to ground to set the power-on reset delay.
DS8007A multiprotocol dual smart card interface ______________________________________________________________________________________ 13 detailed description the following describes the major functional features of the device. use of this document requires the reader have a basic understanding of iso 7816 terminology. parallel bus interface the device interfaces to a host computer/processor through a multiplexed or demultiplexed, parallel, 8-bit data bus (d0?7). the parallel bus interface monitors the ale signal and automatically detects whether a multiplexed or nonmultiplexed external bus interface is intended. the nonmultiplexed external bus interface is the default configuration and is maintained so long as no edge (activity) is detected on the ale pin. once a rising edge is detected on the ale pin, the DS8007A is placed into the multiplexed mode of operation. once in the multiplexed mode of operation, a reset/power cycle or the deassertion of cs forces the device to the non- multiplexed mode. connecting the ale pin to v dd or ground forces the device into nonmultiplexed parallel bus mode. figure 7 shows that the bus recognition dic- tates whether the external address lines (ad3?d0) can be used directly or whether the external data lines (d7?0) must be latched according to the ale input signal. in the multiplexed mode of operation, a new address is latched irrespective of the state of cs . analog interface power-supply supervisor control sequencers iso uart digital interface clock generation timeout counter gndb i/ob c4b c8b presb rstb int cs intaux i/oaux ad0 ad1 ad2 ad3 ale rd wr d0 d1 d2 d3 d4 clkb v ccb gnda i/oa c4a c8a presa rsta clka v cca rstout delay v dd gnd v dda agnd v up dc-dc converter cpa1 cpa2 cpb1 cpb2 d5 d6 d7 xtal1 xtal2 DS8007A figure 6. block diagram
DS8007A multiprotocol dual smart card interface 14 ______________________________________________________________________________________ multiplexed mode in the multiplexed mode of operation, the d7?0 sig- nals are multiplexed between address and data. the falling edge of the address latch enable (ale) signal from the host microcontroller latches the address (d3?0), and the rd and wr strobe input signals are used to enable a read or write operation, respectively, if the DS8007A is selected (i.e., cs = 0). see the ac tim- ing for the multiplexed parallel bus mode found earlier in this data sheet. nomultiplexed mode in the nonmultiplexed mode of operation, the address is always provided on the ad3?d0 signals, and the data is always transacted on the d7?0 signals. the rd input signal is used as a read/write (r/w) operation select. the wr and cs input signals serve as active-low enables, and must be asserted for the read or write operation to take place. see the ac timing for the nonmultiplexed parallel bus mode found earlier in this data sheet. registers 0 ad3?d0 d3?0 d7?0 cs rd wr latch ale cs rst control logic or v dd rst 1 figure 7. parallel bus interface
DS8007A multiprotocol dual smart card interface ______________________________________________________________________________________ 15 * u = unchanged, x = always reflects state of external device pin, even when riu = 0. note: writes to unimplemented bits have no effect. reads of unimplemented bits return 0. table 1. special function register map address (hex) register name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset riu = 0* 00 csr r/w csr7 csr6 csr5 csr4 riu sc3 sc2 sc1 0011 0000 0011 0uuu 01 ccr r/w shl cst sc ac2 ac1 ac0 0000 0000 00uu uuuu 02 pdr r/w pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 0000 0000 uuuu uuuu 03 ucr2 r/w distbe/ rbf disaux pdwn san autoc cku psc 0000 0000 uuuu uuuu 05 gtr r/w gtr.7 gtr.6 gtr.5 gtr.4 gtr.3 gtr.2 gtr.1 gtr.0 0000 0000 uuuu uuuu 06 ucr1 r/w fte0 fip prot t/r lct ss conv 0000 0000 0uuu 00uu 07 pcr r/w c8 c4 1v8 rstin 3v/5v start 0011 0000 0011 uuuu 08 toc r/w toc7 toc6 toc5 toc4 toc3 toc2 toc1 toc0 0000 0000 0000 0000 09 tor1 w tol7 tol6 tol5 tol4 tol3 tol2 tol1 tol0 0000 0000 uuuu uuuu 0a tor2 w tol15 tol14 tol13 tol12 tol11 tol10 tol9 tol8 0000 0000 uuuu uuuu 0b tor3 w tol23 tol22 tol21 tol20 tol19 tol18 tol17 tol16 0000 0000 uuuu uuuu 0c msr r clksw fer bgt cred prb pra intaux tbe/ rbf 0101 0000 u1u1 uuu0 0c fcr w pec2 pec1 pec0 fte1 fl2 fl1 fl0 0000 0000 0uuu 0uuu 0d urr r ur7 ur6 ur5 ur4 ur3 ur2 ur1 ur0 0000 0000 0000 0000 0d utr w ut7 ut6 ut5 ut4 ut3 ut2 ut1 ut0 0000 0000 0000 0000 0e usr r to3 to2 to1 ea pe ovr fer tbe/ rbf 0000 0000 0000 0000 0f hsr r prtlb prtla supl prlb prla intaux ptl 0001 0000 0uuu xxxu control registers special control registers that the host computer/micro- controller accesses through the parallel bus manage most DS8007A features. many of the registers, although only mentioned once in the listing, are dupli- cated for each card interface. the pdr, gtr, ucr1, ucr2, and ccr registers exist separately for each of the three card interfaces. the pcr register is provided only for card interface a and card interface b. the specific register to be accessed is controlled by the current setting of the sc3?c1 bits in the card select register. for example, there are three instances of the uart control register 1 (ucr1) at address 06h. if the sc3?c1 bits are configured so that card a is selected, then all reads and writes to address 06h only affect card a. if sc3?c1 are changed to select card b, then all reads and writes to address 06h only affect card b, etc. in addition, some registers have different functions based on whether the register is being read from or writ- ten to. an example of this are the uart receive (urr)/uart transmit (utr) registers located at address 0dh. although they share the same address, during read operations the receive register is read, and write opera- tions go to a separate transmit register. this selection requires no extra configuration by the software.
DS8007A multiprotocol dual smart card interface 16 ______________________________________________________________________________________ card select register (csr) r = unrestricted read, w = unrestricted write, -n = value after reset. this register is reset to 00110uuub on riu = 0. 76543210 address 00h csr7 csr6 csr5 csr4 riu sc3 sc2 sc1 r-0 r-0 r-1 r-1 rw-0 rw-0 rw-0 rw-0 clock configuration register (ccr) r = unrestricted read, w = unrestricted write, -n = value after reset. this register is reset to 00uuuuuub on riu = 0. 76543210 address 01h shl cst sc ac2 ac1 ac0 r-0 r-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 bits 7 to 4: identification bits (csr7 to csr4). these bits provide a method for software to identify the device as follows: 0011 = DS8007A revision ax bit 3: reset iso uart ( riu ). when this bit is cleared (0), most of the iso uart registers are reset to their initial values. this bit must be cleared for at least 10ns prior to initiating an activation sequence. this bit must be set (1) by software before any action on the uart can take place. bits 2 to 0: select card bits (sc3 to sc1). these bits determine which ic card interface is active as shown below. only one bit should be active at any time, and no card is selected after reset (i.e., sc3?c1 = 000b). other combinations are invalid. 000 = no card is selected. 001 = card a is selected. 010 = card b is selected. 100 = aux card interface is selected. bits 7 and 6: reserved. bit 5: stop high or low (shl). this bit determines if the card clock stops in the low or high state when the cst bit is active. it forces the clock to stop in a low state when shl = 0 or in a high state when shl = 1. bit 4: clock stop (cst). for an asynchronous card, this bit allows the clock to the selected card to be stopped. when this bit is set (1), the card clock is stopped in the state determined by the shl bit. when this bit is cleared (0), the card clock operation is defined by ccr bits ac2?c0. bit 3: synchronous clock (sc). for a synchronous card, the card clock is controlled by software manipu- lation of this sc, and the contact clk is the copy of the value in this bit. in synchronous transmit mode, a write to the utr results in the least significant bit (lsb) of the data written to the utr being driven out on the i/ox pin. in synchronous receive mode, the state of the i/ox pin can be read from the lsb of the urr. bits 2 to 0: alternating clock select (ac2 to ac0). these bits select the frequency of the clock provided to the active card interface and to the uart for the ele- mentary time unit (etu) generation as shown below. all frequency changes are synchronous so that there are no spikes or unwanted pulse widths during transitions. f int is the frequency of the internal oscillator. ac2?c0 000 = f xtal 001 = f xtal / 2 010 = f xtal / 4 011 = f xtal / 8 1xx = f int / 2
DS8007A multiprotocol dual smart card interface ______________________________________________________________________________________ 17 bits 7 to 0: programmable etu divider register bits 7 to 0 (pd7 to pd0). these bits, in conjunction with the defined uart input clock (based upon cku, ac2?c0) and the prescaler selection (psc bit), are used to define the etu for the uart when interfaced to the associated card interface. the output of the prescaler block is further divided according to the pd7?d0 bits as follows: etu = prescaler output / (pd7?d0), when pd7?d0 = 02h?fh etu = prescaler output / 1, when pd7?d0 = 00h?1h prescaler output / 256 is not supported programmable divider register (pdr) r = unrestricted read, w = unrestricted write, -n = value after reset; all bits unaffected by riu = 0. 76543210 address 02h pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 uart control register 2 (ucr2) r = unrestricted read, w = unrestricted write, -n = value after reset; all bits unaffected by riu = 0. 76 5 4 32 1 0 address 03h distbe/rbf disaux pdwn san autoc cku psc r-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 bit 7: reserved. bit 6: disable tbe/rbf interrupt (distbe/rbf). this bit controls whether the tbe/rbf flag can generate an interrupt on the int pin. when this bit is cleared to 0, an interrupt is signaled on the int pin in response to the tbe/rbf flag getting set. when distbe/rbf is set to 1, interrupts are not generated in response to the tbe/rbf flag. disabling the tbe/rbf interrupt can allow faster communication speed with the card, but requires that a copy of tbe/rbf in register msr be polled to not lose priority interrupts that can occur in register usr. bit 5: disable auxiliary interrupt (disaux). this bit controls whether the external intaux pin can generate an interrupt on the int output pin. when this bit is cleared to 0, a change on the intaux input pin results in assertion of the int output pin. when disaux is set to 1, a change on intaux does not result in assertion of the int output pin. the intauxl bit is set by a change on the intaux pin independent of the disaux bit state. since the intaux bit is set independent of the disaux bit, it is advisable to read hsr (thus clearing intaux) prior to clearing disaux to avoid an interrupt on the int pin. to avoid an interrupt when selecting a different card, the disaux bit should be set to 1 in all ucr2 registers.
DS8007A multiprotocol dual smart card interface 18 ______________________________________________________________________________________ bit 4: power-down mode enable (pdwn). this bit controls entry into the power-down mode. power-down mode can only be entered if the supl bit has been cleared. when pdwn is set to 1, the xtal1 and xtal2 crystal oscillator is stopped, and basic functions such as the sequencers are supported by the internal ring oscillator. the uart is put in a suspended state, and the clocks to the uart, the etu unit, and the timeout counter are gated off. during the power-down mode, it is not possible to select a card other than the one cur- rently selected (advisory to the programmer, selecting another card during power-down mode is not recom- mended). there are five ways of exiting the power- down mode: insertion of card a or card b (detected by prla or prlb). withdrawal of card a or card b (detected by prla or prlb). reassertion of the cs pin to select the DS8007A ( cs must be deasserted after setting pdwn = 1 for this event to exit from power-down). intauxl bit is set due to change in intaux (intauxl bit must be cleared first). clearing of pdwn bit by software (if cs pin is always tied to 0). except in the case of a read operation of register hsr, the int pin remains asserted in the active-low state. the host device can read the status registers after the oscillator warmup time, and the int signal returns to the high state. bit 3: synchronous/asynchronous card select (san). this bit selects whether a synchronous or asyn- chronous card interface is enabled. when this bit is cleared to 0, an asynchronous card interface is expect- ed. when this bit is set to 1, a synchronous interface is expected. in synchronous mode, the uart is bypassed; the sc bit controls the clk, and i/o is trans- acted in the lsb of utr/urr. card interface aux can- not operate in the true synchronous mode since it does not have a clk signal to accompany i/oaux. however, the san bit invokes the same control of i/oaux through utr/urr as is given for card interfaces a and b. bit 2: auto convention disable ( autoc ). this active- low bit controls whether the decoding convention should automatically be detected during the first received character in answer-to-reset (atr). if autoc = 0, the character decoding convention is automatically detected (while ss = 1) and the ucr1.conv bit is writ- ten accordingly by hardware. if autoc = 1, the ucr1.conv bit must be set by software to assign the character decoding convention. the autoc bit must not be changed during a card session. bit 1: clock uart doubler enable (cku). this bit enables the effective etu defined for the uart to last half the number of clock cycles defined by the ac2?c0 and pd7?d0 configuration (except in the case when ac2?c0 = 000b, where f clk = f xtal ). when cku is cleared to 0, the ac2?c0 defined f clk is used for etu timing generation. when cku is set to 1, a clock frequency of 2 x f clk is used for etu gener- ation. bit 0: prescaler select (psc). when psc = 0, the prescaler value is 31. when psc = 1, the prescaler value is 32. guard time register (gtr) r = unrestricted read, w = unrestricted write, -n = value after reset; all bits unaffected by riu = 0. 76543210 address 05h gtr.7 gtr.6 gtr.5 gtr.4 gtr.3 gtr.2 gtr.1 gtr.0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 bits 7 to 0: guard time register bits 7 to 0 (gtr.7 to gtr.0). these bits are used for storing the number of guard time units (etu) requested during atr. when transmitting, the DS8007A uart delays these numbers of extra guard time etu before transmitting a character written to utr.
DS8007A multiprotocol dual smart card interface ______________________________________________________________________________________ 19 uart control register 1 (ucr1) r = unrestricted read, w = unrestricted write, -n = value after reset. this register is reset to 0uuu00uub on riu = 0. 76 5 4 32 1 0 address 06h fte0 fip prot t/r lct ss conv r-0 rw-0 r-0 rw-0 rw-0 rw-0 rw-0 rw-0 bit 7: fifo threshold enable 0 (fte0). when this bit and the fte1 (fcr.3) bit are set, the programmable fifo threshold feature is enabled. this bit always reads 0 for compatibility. bit 6: force inverse parity (fip). when this bit is con- figured to 0, the correct parity is transmitted with each character, and receive characters are checked for the correct parity. when fip = 1, an inverse parity bit is transmitted with each character and correctly received characters are nak?. bit 5: reserved. this bit must be left 0. setting this bit to 1 causes improper device operation. bit 4: protocol select (prot). this bit is set to 1 by software to select the asynchronous t = 1 protocol and is cleared to 0 to select the t = 0 protocol. bit 3: transmit/receive (t/r). this bit should be set by software to operate the uart in transmit mode. when this bit is changed from 0 to 1 (uart changed from receive to transmit mode), hardware sets the usr.rbf/tbe bit, indicating an empty transmit buffer. the t/r bit is automatically cleared to 0 following suc- cessful transmission if ucr1.lct is configured to 1 prior to the transmission. this bit cannot be written to when riu = 0 (holding in reset). bit 2: last character to transmit (lct). this bit is optionally set by software prior to writing the last char- acter to be transmitted to the uart transmit register (utr). if lct is set to 1 prior to writing to utr, hard- ware resets the lct, t/r, and tbe/rbf bits following a successful transmission. setting this bit to 1 allows automatic change to the reception mode after the last character is sent. this bit can be set during and before the transmission. this bit cannot be written to when riu = 0 (holding in reset). bit 1: software convention setting (ss). this bit should be set by software prior to atr to allow automat- ic convention detection. hardware automatically resets the ss bit at 10.5 etu after the detection of the start bit of the first character of the atr. bit 0: convention (conv). this bit defines the charac- ter decoding convention of the iso uart. if conv = 1, the convention is direct. if conv = 0, the convention is inverted. if automatic convention detection is enabled ( autoc = 0), hardware detects the character conven- tion and configures the conv bit appropriately at 10.5 etu. otherwise ( autoc = 1), software must configure the conv bit.
DS8007A multiprotocol dual smart card interface 20 ______________________________________________________________________________________ bits 7 to 0: timeout counter configuration register bits (toc7 to toc0). these register bits determine the counting configuration for the three timeout counter registers. the available configurations are detailed in the timeout counter operation section. these registers can be written when riu = 1 before activation and can- not be written to when riu = 0. bits 7 and 6: reserved. bit 5: contact 8 (c8). writes to this register bit are out- put on the c8 pin of the card interface. reads of this register bit reflect the value on the c8 pin. bit 4: contact 4 (c4). writes to this register bit are out- put on the c4 pin of the card interface. reads of this register bit reflect the value on the c4 pin. bit 3: 1.8v card select (1v8). if this bit is set to 1, the v ccx supplied to the card interface is 1.8v. this bit overrides the 3v/5v bit. bit 2: reset bit (rstin). when a card interface is acti- vated, the rstx pin is driven according to the value contained in this register bit. bit 1: 3v/5v card select (3v/5v). this bit determines the v ccx level for the card interface. when this bit is set to 1, v ccx is defined as 3v. when this bit is cleared to 0, v ccx is defined as 5v. when the 1v8 and 3v/5v bits are set to 1, priority is given to 1v8. bit 0: start (start). this bit controls software activa- tion/deactivation of the card interface. when this bit is written to 1, the activation sequence for the selected card is performed. when this bit is written to 0, the deactivation sequence for the selected card is per- formed. hardware automatically resets the start bit for the associated card interface when emergency deactivation occurs. this bit can be written regardless of the state of the riu bit. power control register (pcr) r = unrestricted read, w = unrestricted write, -n = value after reset. this register is reset to 0011uuuub on riu = 0. note: the aux card interface does not have register pcr. c4 and c8 are external ports that are internally pulled up (10k to v ccx ), writing a 1 to c4, c8 configures the weak pullup. reads are made of the pin state to a different physical bit. writing a 0 to c 4, c8 configures the pulldown. c4 and c8 bits can be written irrespective of the state of the t/r bit. 76543210 address 07h c8 c4 1v8 rstin 3v/5v start r-0 r-0 rw-1 rw-1 rw-0 rw-0 rw-0 rw-0 timeout configuration register (toc) r = unrestricted read, w = unrestricted write, -n = value after reset. this register is reset to 00000000b on riu = 0. 76543 210 address 08h toc7 toc6 toc5 toc4 toc3 toc2 toc1 toc0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
DS8007A multiprotocol dual smart card interface ______________________________________________________________________________________ 21 bits 7 to 0: timeout counter register 2 bits (tol15 to tol8). this register can be configured to operate as the lower 8 bits of a 16-bit counter or as the middle 8 bits of a 24-bit counter. see the timeout counter operation section for details on configurable modes. timeout counter register 2 (tor2) r = unrestricted read, w = unrestricted write, -n = value after reset. this register is unchanged on riu = 0. 76543210 address 0ah tol15 tol14 tol13 tol12 tol11 tol10 tol9 tol8 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 timeout counter register 3 (tor3) r = unrestricted read, w = unrestricted write, -n = value after reset. this register is unchanged on riu = 0. 76543 210 address 0bh tol23 tol22 tol21 tol20 tol19 tol18 tol17 tol16 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 bits 7 to 0: timeout counter register 3 bits (tol23 to tol16). this register can be configured to operate as the high 8 bits of a 16-bit counter or as the high 8 bits of a 24-bit counter. see the timeout counter operation section for details on configurable modes. timeout counter register 1 (tor1) r = unrestricted read, w = unrestricted write, -n = value after reset. this register is unchanged on riu = 0. 76543210 address 09h tol7 tol6 tol5 tol4 tol3 tol2 tol1 tol0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 bits 7 to 0: timeout counter register 1 bits (tol7 to tol0). this register can be configured to operate as an 8-bit counter or as the lowest 8 bits of a 24-bit counter. tor1, tor2, and tor3 are concatenated to form a 24- bit etu counter or a pair of independent 16- and 8-bit counters. these counters are only used when a card is supplied an active clock. see the timeout counter operation section for details on configurable modes.
DS8007A multiprotocol dual smart card interface 22 ______________________________________________________________________________________ mixed status register (msr) r = unrestricted read, w = unrestricted write, -n = value after reset. this register is reset to u1u1uuu0b on riu = 0. 76543210 address 0ch clksw fe bgt cred prb pra intaux tbe/rbf r-0 r-1 r-0 r-1 r-0 r-0 r-0 r-0 bit 7: clock switch (clksw). this status bit indicates the clock (f xtal / n or f int / 2) being sourced by the selected card interface and thus may be used to deter- mine when a requested clock switch has occurred properly. when clksw is set 1, the clock has switched from f xtal / n to f int / 2; when clksw is cleared to 0, the clock has switched from f int / 2 to f xtal / n. bit 6: fifo empty status bit (fe). this bit is set to 1 when the receive fifo is empty. this bit is cleared to 0 when at least one character remains in the receive fifo. bit 5: block guard time status bit (bgt). this status bit is linked to an etu counter for the currently selected card interface, and is intended for use in verifying that the block guard time is always being met. the counter restarts on every start bit and stops only if the terminal count is reached. the terminal count is dependent upon the selected protocol (16 etu for t = 0 and 22 etu for t = 1). this bit is cleared to 0 on every start bit. bit 4: control ready (cred). this bit signals the host device that the DS8007A is ready to handle the next write operation to utr or toc or the next read opera- tion of urr. when cred = 0, the DS8007A is still work- ing on the previous operation and cannot correctly process the new read/write request. when cred = 1, the DS8007A is ready for the next read/write request. this ?usy?bit allows the DS8007A to meet the timing constraints of high-speed host devices. the cred bit remains low: 3 clock cycles after the rising edge of rd before reading urr. 3 clock cycles after the rising edge of wr (or cs ) before writing to utr. 1/psc (min) etu and 2/psc (max) etu after the rising edge of wr (or cs ) before writing to toc the cred bit timing applies to asynchronous mode only; this bit is forced to 1 in synchronous mode. bit 3: presence card b (prb). this bit is set to 1 when card b presence is detected and is cleared to 0 when card b is not present. bit 2: presence card a (pra). this bit is set to 1 when card a presence is detected and is cleared to 0 when card a is not present. bit 1: intaux bit (intaux). this bit reflects the state of the intaux pin. this bit is set when the intaux pin is high and is cleared when the intaux pin is low. bit 0: transmit buffer empty/receive buffer full (tbe/rbf). this bit signals special conditions relating to the iso uart and associated hardware. this bit is not set when the last character is transmitted by the uart when lct = 1. this bit is set to 1 when: ucr1.t/r is changed from 0 (receive mode) to 1 (transmit mode). a character is transmitted by the uart. the receive fifo becomes full. this bit is cleared to 0 when: the iso uart is reset by riu = 0. a character is written to the uart transmit register (utr) in transmit mode. a character is read from the receive fifo in receive mode. ucr1.t/r is changed from 1 (transmit mode) to 0 (receive mode).
DS8007A multiprotocol dual smart card interface ______________________________________________________________________________________ 23 uart receive register (urr)/uart transmit register (utr) r = unrestricted read, w = unrestricted write, -n = value after reset. this register is reset to 00000000b on riu = 0. 76543210 address 0dh ur7/ut7 ur6/ut6 ur5/ut5 ur4/ut4 ur3/ut3 ur2/ut2 ur1/ut1 ur0/ut0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 fifo control register (fcr) r = unrestricted read, w = unrestricted write, -n = value after reset. this register is reset to 0uuu0uuub on riu = 0. 76543210 address 0ch pec2 pec1 pec0 fte1 fl2 fl1 fl0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 bits 7 to 0: uart receive register (read operations)/uart transmit register (write operations) (ur7/ut7 to ur0/ut0). this register is used both as the uart transmit and receive buffer by the host microcontroller. received characters are always read by the host microcontroller in direct convention, meaning that if the conv bit is 0, then characters received using inverse convention are automatically translated by the hardware. when the receive fifo is enabled, reads of urr always access the oldest avail- able received data. for the synchronous mode of opera- tion, the lsb (urr.0) reflects the state of the selected card i/ox line. writes by the host microcontroller to this register trans- mit characters to the selected card. the host microcon- troller should write data to utr in direct convention (inverse convention encoding is handled by the hard- ware). the utr register cannot be loaded during trans- mission. the transmission: starts at the end of the write operation (rising edge of wr ) if the previous character has been transmit- ted and the extra guard time has been satisfied. starts at the end of the extra guard time if that guard time has not been satisfied. does not start if the transmission of the previous character is not completed (e.g., during retransmis- sion attempts or if a transmit parity error occurs). for the synchronous mode of operation, only the lsb (utr.0) of the loaded data is transferred to the i/ox pin for the selected card. bit 7: reserved. bits 6 to 4: parity error count (pec2 to pec0). these bits are used only for the t = 0 protocol to determine the number of retransmission attempts that can occur in transmit mode and the number of parity errors that can occur before the pe bit is set to 1 to indicate that the par- ity error limit has been reached. in transmit mode, the DS8007A attempts to retransmit a character up to (pec2?ec0) times (when nak? by the card) before the pe bit is set. retransmission attempts are automati- cally made at 15 etu from the previous start bit. if pec2?ec0 = 000b, no retransmission attempt is made, however, the host device can manually rewrite the char- acter to utr (in which case, it is re-sent as early as 13.5 etu from the previous start bit of the error character. in receive mode, if (pec2?ec0 + 1) parity errors have been detected, the usr.pe bit is set to 1. for example, if pec2?ec0 = 000b, only one parity error needs to be detected for the pe bit to be set; if pec2?ec0 = 111b, 8 parity errors must be detected, etc. if a character is correctly received before the allowed parity error count is reached, the parity counter is reset. for the t = 1 protocol, the parity counter is not used. the pe bit is set whenever a parity error is detected for a received character. bit 3: fifo threshold enable 1 (fte1). when this bit and the fte0 (ucr1.7) bit are set, the programmable fifo threshold feature is enabled. this bit always reads 0 for compatibility. bits 2 to 0: fifo length (fl2 to fl0). these bits determine the depth of the receive fifo. the receive fifo has depth equal to (fl2?l0) + 1 (e.g., fifo depth = 2 if fl2?l0 = 001b).
DS8007A multiprotocol dual smart card interface 24 ______________________________________________________________________________________ bits 7 to 5: timeout counter 3/2/1 status (to3 to to1). these bits are set to 1 whenever their respective timeout counter reaches its terminal count. any of these bits causes the int pin to be asserted. bit 4: early answer detected (ea). this bit is set to 1 if a start bit is detected on the i/o line during the atr between clock cycles 200?68 when the rstx pin is low, and during the first 368 clock cycles after the rstx pin is high. when the ea bit becomes set, int is assert- ed. if the ea bit is set for a card during atr, this bit is cleared when switched to another card. during the early answer detection period, a 46-clock-cycles sam- pling period should be used to detect the start bit; there is an undetected period of 32 clock cycles at the end for both cases (between clock cycles 200?68 when the rstx pin is low, and the first 368 clock cycles after the rstx pin is high). bit 3: parity error (pe). this status bit indicates when the transmit or receive parity error count has been exceeded. for protocol t = 0, the pec2?ec0 bits define the allowable number of transmit or receive pari- ty errors. for protocol t = 1, any parity error results in the setting of the pe bit. when the pe bit is set, int is asserted. for protocol t = 0, characters received with the incorrect parity are not stored in the receive fifo. for protocol t = 1, received characters with parity errors are stored to the receive fifo regardless of the parity bit. the pe bit is set at 10.5 etu in reception mode and at 11.5 etu in transmit mode for t = 0 and t = 1 (pe bit is not applicable for transmit for t = 1). bit 2: overrun fifo (ovr). this status bit is set to 1 if the uart receives a new character when the receive fifo is full. when a fifo overrun condition occurs, the new character received is lost and the previous fifo content remains undisturbed. when the ovr status bit is set, int is asserted. the ovr bit is set at 10.5 etu in receive mode for t = 0 and t = 1. bit 1: framing error (fer). this status bit is set to 1 if the i/o line is not in the high state at time = 10.25 etu after the start bit. the fer bit is set to 10.5 etu in receive mode for t = 0 and t = 1. bit 0: transmit buffer empty/receive buffer full (tbe/rbf). this is a duplicate of the same status bit contained in the mixed status register (msr). uart status register (usr) r = unrestricted read, w = unrestricted write, -n = value after reset. all register bits are reset to 00000000b on riu = 0. note: if any of the bits to3, to2, to1, ea, pe, ovr, or fer are set, then a usr read operation clears the bit, causing an interrupt less than 2? after the rising edge of the rd strobe. pe and fer can be set by the same reception. 76543210 address 0eh to3 to2 to1 ea pe ovr fer tbe/rbf r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0
DS8007A multiprotocol dual smart card interface ______________________________________________________________________________________ 25 hardware status register (hsr) r = unrestricted read, w = unrestricted write, -n = value after reset, x = always reflects state of external device pin. this r egister is reset to 0uuuxxxub on riu = 0. note: a minimum of 2? is needed between successive reads of the hsr to allow for hardware updates. in addition, a minimum of 2? is needed between reads of the hsr and activation of card a, card b, or the aux card. 76543210 address 0fh prtlb prtla supl prlb prla intauxl ptl r-0 r-0 r-0 r-1 r-0 r-0 r-0 r-0 bit 7: reserved. bit 6: protection card interface b status bit (prtlb). this bit is set to 1 when a fault has been detected on card reader interface b. a fault is defined as detection of a short-circuit condition on either the rstb or v ccb pin as given by dc specs i rst(sd) and i cc(sd) . the int signal is asserted at logic 0 (active) while this bit is set. this bit returns to 0 after any hsr read, unless the condition persists. bit 5: protection card interface a status bit (prtla). this bit is set to a 1 when a fault has been detected on card reader interface a. a fault is defined as detection of a short-circuit condition on either the rsta or v cca pin as given by dc specs i rst(sd) and i cc(sd). the int signal is asserted at logic 0 (active) while this bit is set. this bit returns to 0 after any hsr read, unless the condition persists. bit 4: supervisor latch (supl). this bit is set to 1 when v dd < v rst or when a reset is caused by exter- nally driving the delay pin < 1.25v. at this time the int signal is asserted at logic 0 (active). this bit returns to 0 only after an hsr read outside the alarm pulse. bit 3: presence latch b (prlb). this bit is set to 1 when a level change has been detected on the presb pin of card interface b. the int signal is asserted at logic 0 (active) while this bit is set. this bit returns to 0 after any hsr read. bit 2: presence latch a (prla). this bit is set to 1 when a level change has been detected on the presa pin of card interface a. the int signal is asserted at logic 0 (active) while this bit is set. this bit returns to 0 after any hsr read. bit 1: intaux latch (intauxl). this bit is set to 1 when a 0 1 or a 1 0 level change has been detect- ed on the intaux pin. this bit remains set, regardless of further level changes on the intaux pin until cleared to 0 by any hsr read. bit 0: protection thermal latch (ptl). this bit is set to 1 when excessive heating (approximately +150? or greater) is detected. the int signal is asserted at logic 0 (active) while this bit is set. this bit returns to 0 after any hsr read, unless the condition persists.
DS8007A multiprotocol dual smart card interface 26 ______________________________________________________________________________________ card interface voltage regulation and step-up converter operation the v dd and v dda pins supply power to the DS8007A. voltage supervisor circuitry detects the input voltage levels and automatically engages a step-up converter if necessary to generate the appropriate voltages to the card interfaces according to the control register set- tings. the conversion process is transparent to the user and is usually only noticed by changes in the v up pin voltage, which reflects the operation of the internal charge pump. table 2 elaborates on the v up pin. the v dd and v dda pins must be decoupled externally, but extra care must be taken to decouple large current spikes that can occur on the v dda pins because of noise generated by the cards and internal voltage step- up circuitry. voltage supply supervision the voltage supervisor circuitry monitors v dd and holds the device in reset until v dd is at a satisfactory level. the delay pin is an external indicator of the state of internal power and can also be driven external- ly to hold the device in a reset state. an external capac- itor is usually attached to this pin, defining the time constant of a power-on delay for the DS8007A. when v dd is below the voltage threshold v rst , the charging path that exists between v dd and delay is discon- nected and a strong pulldown is enabled on the delay pin. once v dd exceeds v rst , the strong pulldown on the delay pin is released and the pullup to v dd is enabled, allowing the external delay capacitor to be charged. the rstout alarm pin is released (allowing it to be pulled up externally) whenever the delay pin voltage is less than v drst , whether caused by v dd < v rst or as a result of external hardware pulling the delay pin low. the minimum duration of the rstout pulse (t w specification) is defined by the capacitor connected to the delay pin and is typically 1ms per 2nf. the rstout pin is driven strongly low once the delay pin exceeds the v drst voltage threshold. the supl bit is set on initial power-up and is reset again when the rstout alarm pulse occurs. the supl bit may only be cleared by a read of the hsr register. figure 8 illustrates the sequencing of the various sig- nals involved. short-circuit and thermal-protection circuitry prevent damages done by accidentally shorting the v ccx pins or when the ambient temperature is exceeding the maximum operating temperature. when the internal temperature is approximately +150?, the voltage v ccx and the drivers to the clkx, rstx, i/ox, c4x, and c8x signals to both card interfaces are turned off. the ptl bit in the hsr is set and an interrupt is generated. when a short is detected on the rstx pin, the device initiates a normal deactivation sequence. a short on i/ox, c4x, and c8x does not cause deactivation. voltage (v) v dda smart card v up < 2.4 x v dda 2.4?3.5 5 5.7 3.5?5.5 5 5.7 5.5?6.0 5 v dda 2.4?3.5 3.0 4.1 > 3.5 3.0 v dda 2.4?6.0 1.8 v dda table 2. step-up converter operation
DS8007A multiprotocol dual smart card interface ______________________________________________________________________________________ 27 v dd delay rstout int supl bit v rst = 2.1v to 2.5v v drst = ~1.25v resulting from v dd < v rst delay driven low externally supl bit cleared by hsr read only t w figure 8. voltage supervisor
DS8007A multiprotocol dual smart card interface 28 ______________________________________________________________________________________ start bit rstin bit rstx v up v ccx clkx i/0x c4x, c8x activation sequence 1. pcrx.start bit is set by software. conditions needed (in hardware) are: msr.prx = 1 (card x present) hsr.prtlx, supl, prlx, ptl = 0 2. step-up converter activated (may already be on if another card was active). 3. v ccx enabled to 1.8v, 3v, or 5v as selected by pcrx.1v8 and pcr.3v/5v bits. v ccx rises from 0v to 1.8v, 3v, or 5v with a controlled rise time of 0.17v/ s typical. 4. i/ox is pulled high. c4x, c8x are also pulled high if pcrx.c4 = 1, pcrx.c8 = 1 (respectively). these pins have integrated pullups (14k for i/ox and 10k for c4x and c8x) to v ccx . 5. clkx output is enabled and rst output is enabled. (pcrx.rstin should be "0" for active-low rstx.) 6. pcrx.rstin written to "1" by software after using toc to time sufficient duration of rstx pin assertion. deactivation sequence 1. pcrx.start bit is cleared by software. 2. the active-low rstx signal is asserted by software. 3. the clkx signal is stopped. 4. i/ox, c4x, and c8x fall to 0v. 5. v ccx is disabled and falls to 0v with a typical rate of 0.17v/ s. 6. step-up converter is deactivated if not in use by another card and pins clkx, rstx, i/ox, and v ccx become low impedance to ground. timing according to pcrx.c4, pcrx.c8 bits v ccx needs to decrease to less than 0.4v activation needs to occur in under 130 s activation sequence deactivation sequence t act t de 1234 5 123 45 6 6 t0 t1 t2 t3 t4 t5 t10 t11 t12 t13 t14 t15 undefined ts t0 figure 9. card activation, deactivation sequences activation sequencing an activation sequence can only be requested by a host device through the parallel bus interface. the host can request an activation sequence for a specific card (card a or card b) by setting the start bit of the pcrx register (where x = a or b as determined by the card select scx bits of the csr). the host software can acti- vate both cards at the same time, but only one card can be selected to transmit/receive at a given time. the activation sequence can only occur given satisfactory operating conditions (e.g., the card is present and the supply voltage is correct). these conditions can be ascertained through the hsr, msr, and csr bits. if the microcontroller attempts to write the pcrx.start bit to 1 without having satisfied the necessary condi- tions, the card is not activated and the bit does not change. the activation time (from the assertion of the start bit until the clock output is enabled) is less than 130?. the activation sequence is detailed in figure 9.
DS8007A multiprotocol dual smart card interface ______________________________________________________________________________________ 29 deactivation sequencing the host device can request a deactivation sequence by resetting the start bit to 0 for the desired card interface. the deactivation (from the deassertion of the start bit, step 1 of the deactivation sequence, to v ccx decrease to less than 0.4v) is less than 150?. emergency deactivation an emergency deactivation occurs if unsatisfactory operating conditions are detected. an emergency deac- tivation occurs for all activated cards in response to a supply-voltage brownout condition (as reported by the hsr.supl bit) or chip overheating (as reported by hsr.ptl). emergency deactivation of an individual card can occur if a short-circuit condition is detected on the associated v ccx or rstx pin (as reported by hsr.prtlx) or in the case of a card takeoff (as reported by hsr.prlx). when an emergency deactivation occurs, hardware automatically forces the associated start bit(s) to the 0 state. the response of the device to the emergency deactivation varies according to the source. if the rstx pin is shorted or the device overheats, the sequencer executes a fast emergency deactivation sequence, which ramps down v ccx immediately. if the v ccx pin was shorted, the sequencer executes a deactivation sequence in same way as if the start bit was cleared to 0. interrupt generation the int output pin signals the host device that an event occurred that may require attention. the assertion of the int pin is a function of the following sources: a fault has been detected on card interfaces (a or b). ? dd has dropped below the acceptable level. a reset is caused by externally driving the delay pin to less than 1.25v. excessive heating is detected (i.e., ptl = 1). a level change has been detected on pin presx or intaux for the card interfaces (a, b, or aux). the parity and/or frame error is detected. the early answer (ea) bit is set during atr. the timeout counter(s) reach their terminal count(s). the fifo full status is reached. the fifo overrun occurs. the transmit buffer is empty. hsr.prtla hsr.prtlb hsr.prla hsr.prlb hsr.ptl hsr.supl usr.to3 usr.to1 usr.to2 usr.ea usr.ovr usr.fer usr.pe hsr.intauxl interrupt generation int output pin sca, scb, scaux ucr2a.disaux ucr2b.disaux ucr2aux.disaux ucr2a.distbe/rbf usr.tbe/rbf ucr2b.distbe/rbf ucr2aux.distbe/rbf sca, scb, scaux figure 10. interrupt sources
DS8007A multiprotocol dual smart card interface 30 ______________________________________________________________________________________ timeout counter operation the timeout counter assists the host device in timing real-time events associated with the communication pro- tocols: the work wait time (wwt), block waiting time (bwt), etc. the timeout counter registers count etus, so the input clock to the timeout counter is derived from the output of the programmable divided clock (per card pdr register). the timeout counter requires the card be pow- ered and have an active clock. the timeout counter can operate as a single 24-bit counter (tor3?or1) or as separate 16-bit (tor3?or2) and 8-bit (tor1) counters. the timeout counters can be operated in either software mode or start bit mode. the software mode is supported for the 16-bit and 24-bit counters. the start-bit mode is sup- ported for all counter widths (8 bit, 16 bit, and 24 bit). see table 3. software mode in software mode, software configures the counter to a starting value (while stopped) and starts the down counter by writing the configuration value to the toc register. when the terminal count is reached (0h), the counter stops, the timeout flag is set, and an interrupt is generated. if the software counter does not reach the terminal count, it must be stopped before loading a new value into the associated torx counter registers. it is possible to stop and start the 16-bit software counter while leaving the 8-bit counter enabled (e.g., toc = 65h ? 05h, toc = e5h ? 85h, etc.). if a compatible software mode command is written to the toc register before the terminal count is reached (e.g., write 61h to toc register while the 65h toc command is running or vice versa), the new command is ignored (still software mode), but the toc register is updated with the new command, and the counter continues to count until the terminal count is reached, the respective timeout flag(s) is set, and an interrupt is generated. start-bit mode when configured to start-bit mode, counting starts (and restarts for the 16-bit and 24-bit counters) when a start bit is detected on the active card interface i/ox pin. when the terminal count is reached, the 8-bit autoreload counter begins counting from the previously programmed start value, while a 16-bit counter or 24-bit counter stops when terminal count is reached. if the terminal count is reached, the timeout flag is set and an interrupt is generated. the 8-bit autoreload tor1 regis- ter cannot be modified during a count. the 16-bit and 24-bit counter registers can be modified during a count without affecting the current count. the new register data is used on the next start bit detection. table 3. timeout counter configurations toc value tor3 tor2 tor1 description 00h stopped all counters are stopped. 05h stopped start bit/autoreload counters 3 and 2 are stopped. counter 1 continues in start- bit/autoreload mode for both transmission and reception. 61h software stopped counter 1 is stopped. counters 3 and 2 form a 16-bit counter operating in software mode. the counter is stopped by writing 00h to the toc register, and must be stopped before reloading new values in tor3 and tor2 registers. 65h software start bit/autoreload counters 3 and 2 form a 16-bit counter operating in software mode. writing 05h to the toc register before reloading new values in tor2/tor3 stops the counters. counter 1 is operated in start- bit/autoreload mode. the tor1 register may not change during the count. the 16-bit counters are stopped by setting toc = 05h. both counters are stopped by setting toc = 00h. 68h software counters 1, 2, and 3 form a 24-bit counter operating in software mode. the counter starts after the command is written to the toc register, and is stopped by setting toc = 00h. tor3, tor2, tor1 cannot be changed without stopping the counter first.
DS8007A multiprotocol dual smart card interface ______________________________________________________________________________________ 31 table 3. timeout counter configurations (continued) toc value tor3 tor2 tor1 description 71h start bit stopped counter 1 is stopped. counters 3 and 2 form a 16-bit counter operating in start bit mode for both transmission and reception. tor3 and tor2 registers can be changed during the count, the current count is not affected, and the values are taken into account at the next start bit detected on the i/ox pin. setting toc = 00h stops the counters. 75h start bit start bit/autoreload counter 1 is an 8-bit counter in start-bit/autoreload mode for both transmission and reception; counters 3 and 2 form a 16-bit counter operating in start-bit mode for both transmission and reception. the tor1 register is not allowed to change during the count. tor3, tor2 registers can be changed during the count, the current count is not affected, and the values are taken into account at the next start bit detected on the i/ox pin. setting toc = 00h stops the counters. 7ch start bit counters 1/2/3 form a 24-bit counter operating in start-bit mode in both transmission and reception. tor3, tor2 and tor1 registers can be changed during the count, the current count is not affected, and the value is taken into account at the next start bit detected on the i/ox pin. setting toc = 00h stops the counter. 85h stopped start bit/autostop (rcv); start bit/autoreload (xmt) counters 3 and 2 are stopped. counter 1 is operated in start- bit/autostop mode in reception and is stopped at the end of the 12th etu following the first received start bit detected on the i/ox pin unless the terminal count is reached first. counter 1 operates in start-bit/autoreload mode in transmission. e5h software start bit/autostop (rcv); start bit/autoreload (xmt) counters 3 and 2 form a 16-bit counter operating in software mode. the counters are stopped by setting toc = 05h before reloading new values in tor3 and tor2 registers. counter 1 is operated in autostop mode in reception and is stopped at the end of the 12th etu following the first received start bit detected on the i/ox pin unless the terminal count is reached first. counter 1 is operated in start-bit/autoreload mode in transmission. f1h start bit/autostop (rcv); start bit (xmt) stopped counter 1 is stopped. counters 3 and 2 form a 16-bit counter. the 16-bit counter is operated in start-bit/auto-stop mode in reception and is stopped at the end of the 12th etu following the first received start bit detected on the i/ox pin unless the terminal count is reached first; and the 16-bit counter is operated in start-bit mode in transmission. f5h start bit/autostop (rcv); start bit (xmt) start bit/autostop (rcv); start bit/autoreloa d (xmt) counter 1 is an 8-bit counter operating in start-bit/autostop mode in reception and is stopped at the end of the 12th etu following the first received start bit detected on the i/ox pin unless the terminal count is reached first; and the 8-bit counter is operated in start-bit/autoreload mode in transmission. counters 3 and 2 form a 16-bit counter operating in start-bit mode for transmission but operate in start-bit/autostop mode in reception. counters 3 and 2 are stopped at the end of the 12th etu following the first received start bit detected on the i/ox pin unless the terminal count is reached first; the counters are stopped by setting toc = 00h.
DS8007A multiprotocol dual smart card interface 32 ______________________________________________________________________________________ iso uart implementation reset operation the hsr.riu control bit resets the iso uart. the hsr.riu must be reset prior to any activation. hsr.riu must be returned to 1 by software before any uart action can take place. synchronous mode the synchronous mode of operation is invoked by set- ting the synchronous/asynchronous card select bit (for a given card interface) to logic 1. in the synchronous mode of operation, the associated i/ox card interface data is transferred by the lsb of the uart transmit/receive registers (utr and urr). in this mode, the host device using the ccrx.sc register bit manual- ly controls the clkx pin for the selected card interface. switching to the synchronous mode or vice versa is allowed at any time when the card is active. however, it is the responsibility of the host software/firmware to ensure that the current transmission is concluded before switching. if software configures an active card for synchronous mode, and then activates another card, the i/o pin on the previously active card goes to a high-impedance state with a weak pullup (high). the newly selected interface (if configured to synchronous mode) takes on utr.0. the aux card interface does not have an associated clk signal, so the ccraux.sc bit does not control an output signal when the synchronous mode of operation is in effect. the handshake between the host and the auxiliary smart card interface is accomplished through the auxiliary interrupt input (intaux) and the int pins. the msr.intaux bit reflects the state of the intaux pin. if the ucr2.disaux bit is cleared to 0, a change on the intaux input pin results in the assertion of int output pin. the host software/firmware establishes the commu- nication protocol and controls when to transmit/receive data in response to the interrupt. if the ucr2.disaux bit is set to 1, the int pin is not asserted, and the host soft- ware/firmware must examine the intaux bit in the msr register and responds accordingly. asynchronous mode the asynchronous mode of operation is the reset default mode for all card interfaces and is selected when the synchronous/asynchronous card select bit (for a given card interface) is configured to logic 0. the i/ox card interface signal is used for asynchronous half-duplex data communication between the host-con- trolled iso uart and the external smart card. the host device can optionally stop the clkx signal in the high or low state while the card is active using the ccrx.cst and ccrx.shl register bits. etu generation and timing the basic unit of time for asynchronous mode commu- nication on the i/ox signal is the elementary time unit (etu). the etu is defined within the iso uart as a function of the f clk frequency that is configured for the card interface (i.e., the same f clk that can be sourced to the clkx pin of an associated card interface a or b). in addition to receiving f clk from the clock generation block, the iso uart additionally receives a 2 x f clk frequency if ccrx.ac2?c0 000b. the host device can select whether f clk or 2 x f clk is used for etu generation by using the clock uart (cku) select bit. when cku = 0, f clk is used, while 2 x f clk is used when cku = 1. one exception exists when ccrx.ac2?c0 = 000b, in which case, only f clk is sourced to the uart and the cku bit setting has no effect on the duration of an etu. the basic clock that is selected for etu generation by the cku bit is further prescaled by a factor or 31 or 32. the prescaler select control (psc) bit makes this prescaler selection. when psc is configured to logic 0, the prescale setting is 31. when psc is configured to logic 1, the prescale setting is 32. the output of the clock prescaler drives an 8-bit autoreload down counter. the autoreload value for the downcounter is configured by the host device through the programmable divider register (pdr). the interval pro- vided by this downcounter defines the etu duration for the selected card. figure 11 shows a diagram of etu generation. all the asynchronous character transmit/receive operations are defined in terms of etu (e.g., 10.5 etu, 10.25 etu, etc).
DS8007A multiprotocol dual smart card interface ______________________________________________________________________________________ 33 standard clock frequencies and baud rates the DS8007A supports i/o communication and clkx frequency generation compliant to the following stan- dards: iso 7816, emv2000, and gsm11-11. each of these standards has an allowable clkx frequency range and a defined relationship between clkx fre- quency and etu (baud rate) generation that is support- ed initially and after negotiation. for iso 7816, the relationship between etu (baud rate) timing and clkx frequency is as follows: etu = (f / d) x (1 / f clkx ) the minimum clkx frequency is fixed at 1mhz. the default maximum clkx frequency is 5mhz, however the maximum clkx frequency can be increased according to the fi parameter given by the card during atr. the iso 7816-1997(3) specification recommends in section 4.3.4 that clkx frequency switches be made a) immediately after atr or b) immediately after a suc- cessful pps exchange. the transmission parameters f and d are respectively the clock-rate conversion and baud-rate adjustment factors. the notations fd and dd are used to represent the ??fault values for these parameters, which are fd = 372 and dd = 1. the nota- tion fi and di are used to represent the values ??dicat- ed by the card within the ta(1) character of atr. if ta(1) is not present, then fi,di are set to the default fd,dd values. the notation fn and dn represent values ??gotiated during a successful pps exchange, which should be in the range fd-fi and dd-di, respectively. during atr, the default fd, dd values shall apply. if the card comes up in negotiable mode (i.e., ta(2) is absent from the atr), then the fd, dd parameters con- clock prescaler pdr /31: psc = 0 /32: psc = 1 pd7:pd0 = 00h to ffh clock prescaler gate pdr /31: psc = 0 /32: psc = 1 pd7:pd0 = 00h to ffh clr (aligned etu generator) ucr2x.psc software mode to3, to2, to1 10.5 etu to 15 etu 10.25 etu etu etu en toc counters clk en fractional etu counters clk en frame-error- detected counter clk 0.5etu 0.25etu clr ucr2x.cku f clk 0 1 1 0 2 x f clk rstx start bit figure 11. etu generation
DS8007A multiprotocol dual smart card interface 34 ______________________________________________________________________________________ tinue to be used until a successful pps exchange is completed. the negotiated fn, dn values are then used after a successful pps exchange. if the card comes up in specific mode (i.e., ta(2) is present in atr), then the indicated fi, di values apply immediately after suc- cessful atr if bit 5 of the ta(2) character is 0. if bit 5 of ta(2) is 1, implicit values should be used. the ta(1) character of atr, if present, contains the fi and di val- ues indicated by the card. table 5 demonstrates how the prescaler (psc) bit and programmable divider register (pdrx) can be config- ured to generate the requested f/d ratios. all settings assume that the cku bit is configured to its reset default logic 0 state. table 4. fi, di parameter possibilities ta(1).fi fi max clkx (mhz) fi = ta(1).di di 0000 372 4 31 x 12 0000 rfu 0001 372 5 31 x 12 0001 1 0010 558 6 31 x 18 0010 2 0011 744 8 31 x 24 0011 4 0100 1116 12 31 x 36 0100 8 0101 1488 16 31 x 48 0101 16 0110 1860 20 31 x 60 0110 32 0111 rfu ? ? 0111 rfu 1000 rfu ? ? 1000 rfu 1001 512 5 32 x 16 1001 12 1010 768 7.5 32 x 24 1010 20 1011 1024 10 32 x 32 1011 rfu 1100 1536 15 32 x 48 1100 rfu 1101 2048 20 32 x 64 1101 rfu 1110 rfu rfu ? 1110 rfu 1111 rfu rfu ? 1111 rfu rfu = reserved for future use. table 5. psc, pdr settings to support f,d parameters pdr setting for di = ta(1).fi psc 0 = /31 1 = /32 0001 0010 0011 0100 0101 0110 1000 1001 0000 0 12 6 3 ? ? ? 1 ? 0001 0 12 6 3 ? ? ? 1 ? 0010 0 18 9 ? ? ? ? ? ? 0011 0 24 12 6 3 ? ? 2 ? 0100 0 36 18 9 ? ? ? 3 ? 0101 0 48 24 12 6 3 ? 4 ? 0110 0 60 30 15 ? ? ? 5 3 1001 1 16 8 4 2 1 ? ? ? 1010 1 24 12 6 3 ? ? 2 ? 1011 1 32 16 8 4 2 1 ? ? 1100 1 48 24 12 6 3 ? 4 ? 1101 1 64 32 16 8 4 2 ? ?
DS8007A multiprotocol dual smart card interface ______________________________________________________________________________________ 35 character encoding/ decoding convention the iso uart is designed to support two possible char- acter encoding/decoding formats: direct and inverted. the direct character coding convention transmits and receives data lsb first and associates a high logic level with a bit 1 and a low logic level with a bit 0. the inverse character coding convention transmits and receives data most significant bit first and associates a high logic level with a bit 0 and a low logic level with a bit 1. the ucr1.conv bit defines which character conven- tion (conv = 0:inverse; conv = 1:direct) should be used by the iso uart. the ucr1.conv bit can be configured by the host device software or be config- ured by hardware if automatic convention detection has been enabled. automatic convention detection the automatic convention detection relies upon recog- nition of a predefined pattern in the first character received (ts character) in atr for establishing future character coding convention. to enable automatic con- vention detection, the ucr1.ss bit must be set to logic 1 and the ucr2. autoc bit should be configured to logic 0 prior to atr. the ss bit is automatically cleared by hardware 10.5 etu after the character is received. if automatic convention detection is enabled and an unrecognized character is received, the conv bit is not written. if neither the direct nor inverse character are detected, a parity error occurs along with error sig- nal generation for the t = 0 protocol. the autoc bit should not be modified during a card session. framing error detection the DS8007A monitors the selected card i/ox signal at 10.25 etu following each detected start bit. if the i/ox signal is not in the high state at this point in time, the usr.fer (framing error) bit is set to 1 at 10.5 etu. the fer bit is cleared to 0 whenever usr is read. ts character (conveys coding convention) direct convention (byte = 3bh) inverse convention (byte = 3fh) lsb 11 11 1 1 0 0 0 00 11 1 0 1 1 1 msb msb lsb figure 12. direct, inverse character coding conventions iso uart urr i/oa i/ob i/oaux f clkx 2 x f clkx start detect etu fifo(8) utr pdr.pd[7:0] gtr.gtr.[7:0] ucr1 ucr2 csr.riu msr.fer msr.bgt msr.tbe/rbf usr.ea fcr.pec[2:0] fcr.fl[2:0] usr.pe usr.ovr usr.fer figure 13. iso uart signal interface
DS8007A multiprotocol dual smart card interface 36 ______________________________________________________________________________________ block guard time the block guard time for the asynchronous serial com- munication between the smart card reader (DS8007A) and the icc is defined as the minimum delay between consecutive start bits sent in the opposite direction. the DS8007A implements an internal etu counter specifically to help the host device assess that this min- imum block guard time is being met. this internal etu counter is loaded on each start bit with the value 22d or 16d, dependent upon the protocol selected. for t = 0, the counter is loaded with the value 16d and for t = 1, the counter is loaded with the value 22d. if the counter reaches 0, the msr.bgt status bit is set and the counter stops. if a start bit is detected before the counter reaches 0, the counter is reloaded and the bgt status bit is cleared to 0. transmit mode the iso uart transmit mode is invoked by setting the associated ucr1.t/r bit to logic 1. when the iso uart is placed into transmit mode, the tbe/rbf bit is set to 1 to indicate that the transmit buffer is empty. when a character is written to utr register, the tbe/rbf bit is cleared to indicate that the transmit buffer is no longer empty. if the transmit serial shift reg- ister is available (which is the case unless character retransmission is occurring), the character is translated according to the character coding convention (conv bit) and moved from the transmit buffer to the serial shift register. the tbe/rbf bit returns high so that another character can be loaded into the utr register. guard time some smart cards require extra time to handle informa- tion received from an interface device. to allow this extra time, the DS8007A implements a guard time register (gtr) per card interface. this register is pro- grammed with the number of extra etu that should be enforced between consecutive start bits transmitted by the DS8007A (discounting retransmissions at the request of the icc). the gtr register defaults to 00h on reset, indicating that no extra guard time is required (i.e., 12 etu must be enforced between transmission of consecutive start bits). if the gtr register is pro- grammed to ffh, the delay required between consecu- tive start bits is dependent upon the protocol selected (per ucr1.prot). gtr = ffh t = 0 protocol: 11.8 etu t = 1 protocol: 10.8 etu block guard time (bgt) counter and status bgt counter 0: - clear bgt bit - restart bgt counter (e.g., 16 etu for t = 0) bgt counter = 0 (stopped): set bgt bit bgt bit i/ox figure 14. block guard time etu counter operation
DS8007A multiprotocol dual smart card interface ______________________________________________________________________________________ 37 last character to transmit the iso uart implements a special control input that allows an automatic switch from transmit mode (ucr1.t/r = 1) to receive mode (ucr1.t/r = 0) upon successful character transmission. the last character to transmit (ucr1.lct) bit must be set to 1 by host software prior to writing the last character for transmis- sion to utr. upon successful transmission of the char- acter, the ucr1.t/r bit and the lct bit are cleared by hardware. when the lct bit is used, the tbe/rbf bit is not set at the end of the transmission. receive mode the iso uart receive mode is in effect if the associat- ed ucr1.t/r bit is 0. when the iso uart is changed to receive mode, the msr.fe bit is set to 1 to indicate that the receive fifo is empty. when at least one unread receive character exists in the fifo, the fe bit is cleared. when the fifo, with depth defined by fl2?l0, is full, the tbe/rbf bit is set to 1 to indicate that the receive buffer is full. once a character is read from a full fifo, the rbf/tbe bit is cleared to indicate that the fifo is no longer full. the controller ready (cred) bit should be polled to assess data readiness when reading from register urr at high frequencies. parity check the t = 1 protocol selection checks receive parity. for t = 1, the parity error count bits (pec2?ec0) have no function and the usr.pe bit are set on the first parity error. the t = 0 protocol selection also checks receive parity, but allows setting of the usr.pe parity error bit to be based upon detection of 1? parity errors. the pec2?ec0 bits define the number of consecutive par- ity errors that should be detected before setting usr.pe. the iso uart implements a special control input that allows testing for inverse parity. if the ucr1.fip bit is configured to 0 during receive mode, the iso uart tests for correct parity on each received character. if ucr1.fip is configured to 1, inverse parity is expected. this control can be useful in testing that the icc prop- erly detects error signals generated by the DS8007A and retransmits requested characters. lct bit written to 1 by software, then load utr. last character to transmit tbe remains 0, lct and t/r bits are both cleared to 0 by hardware. p last character last character i/o tbe/rbf bit lct bit t/r bit p figure 15. last character to transmit
DS8007A multiprotocol dual smart card interface 38 ______________________________________________________________________________________ error-signal generation the t=1 protocol does not support error-signal genera- tion. when configured to receive using the t = 0 proto- col (ucr1.prot = 0), the DS8007A supports error- signal generation in response to parity. the parity error count bits (pec2?ec0) of the fifo control register (fcr) determine the number of allowed repetitions in reception, and therefore the number of times that an error signal is generated in response to a received character with incorrect parity before the usr.pe bit becomes set. when receiving a character, the DS8007A verifies even parity for the combination of the received 8-bit charac- ter and parity bit. if incorrect parity is determined and consecutive parity error counter has not reached termi- nal count (000b), the DS8007A generates an error sig- nal on the i/ox line starting at 10.5 etu and lasting for 1.0 etu. the parity error counter is initialized through the pec2?ec0 bits. configure the pec2?ec0 bits to 000b means that no repetition in reception is allowed and that an error signal generation occurs in response to a character received with incorrect parity. configuring pec2?ec0 bits to 001b means one repe- tition in reception is allowed and that the DS8007A gen- erates an error signal only once per character receive attempt. when the consecutive parity error counter reaches 000b and a character is received with incor- rect parity, the usr.pe bit is set to 1. if the parity error counter has not reached terminal count, it is reset to the originally programmed value upon reception of a char- acter having the correct parity. once the usr.pe bit signals a parity count error, the software must re-estab- lish any nonzero pec2?ec0 setting. receive fifo the DS8007A implements an enhanced receive fifo. if the fifo threshold-enable bits fte0 and fte1 are set to 0, the fifo functions as a standard fifo that is con- figurable to a depth of 1 to 8 characters. the t = 0 and t = 1 protocols allow the fifo depth to be determined by the fcr.fl2?cr.fl0 bits. when configurable, the fifo depth is equal to (fl2?l0) + 1 (e.g., fl2?l0 = 001b configures the fifo depth to 2). the rbf/tbe and fe status bits report the full and empty fifo condi- tions, respectively. if the receive fifo is full (at a maxi- mum depth of 8), the fifo overrun (ovr) bit is set to 1, the new character received is lost, and the previous fifo contents remain undisturbed. the received characters are read from the urr. when the receive fifo is enabled, reads of the urr always access the oldest available received data. the fifo is initialized every time the receive mode is invoked (i.e., t/r bit is cleared to 0). character n error-signal generation (t = 0 protocol only) parity bit does not check if (incorrect parity and pec 000b) hardware error signal at 10.5 etu?1.5 etu and decrement parity counter. if (correct parity and pe = 0) reset parity error counter to original pec2?ec0 programmed value. etu time => 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 p p character n (retransmit) figure 16. receive mode?rror signal generation
DS8007A multiprotocol dual smart card interface ______________________________________________________________________________________ 39 for the t = 0 protocol, only received characters without parity errors are stored in the receive fifo. when ucr1.fip = 1 during t = 0 reception, only those char- acters with incorrect parity are stored to the receive fifo since the DS8007A is checking for inverse parity. for the t = 1 protocol, the receive character is stored to the fifo no matter whether the parity checks cor- rectly or not. if the fifo threshold enable bits fte0 and fte1 are set to 1, the fifo implements a programmable threshold for the assertion of the rbf/tbe bits and the interrupt line. in this mode, the internal fifo length is forced to 8 bytes, and fl[2:0] (the programmable fifo length bits) determines the threshold value. characters are accumulated in the fifo without setting the rbf/tbe bits until the fifo depth is greater than the threshold value. as long as the used depth is greater than the fl[2:0] value, the rbf/tbe bits (usr and msr) are set and the interrupt pin is asserted. reading the fifo to a level less than or equal to the threshold value resets the rbf/tbe bit and deasserts the interrupt line. writing a zero or eight into the fl bits while the pro- grammable threshold mode is enabled causes the fifo to behave as it does in nonprogrammable thresh- old mode. if the programmable fifo depth is at its maximum (8 characters) the rbf/tbe bit is set when the eighth character is received and written into the fifo. if anoth- er character is received while the fifo is full, the over- flow (ovr) status is set, and the new character overwrites the previously received character. if the programmable fifo depth is set to zero, the receipt of a single character sets rbf/tbe. receiving another character in this state sets the ovr bit and overwrites the character. the fifo empty status bit (fe) operates as before. the programmable threshold feature functions the same in t = 0 and t = 1 modes. early answer (ea) if a start bit is detected on the i/o line during the atr between clock cycles 200?68 when the rstx pin is low and during the first 368 clock cycles after the rstx is high, it is recognized as an early answer (ea), and the ea bit is set in the usr.ea register. when the ea bit is set, int is asserted. during the early answer detection period, 46 clock cycles sampling periods should be used to detect the start bit and there is an undetected (uncertainty) period of 32 clock cycles at the end for both cases (between clock cycles 200?68 when the rstx pin is low, and the first 368 clock cycles after rstx is high). table 6 summarizes the status of the early answer bit. the answer on the i/o line begins between 400 and 40,000 clock cycles after the rising edge of the rstx signal. development and technical support the ds8007 evaluation kit (ev kit) is available to assist in the development of designs using the ds8007/DS8007A multiprotocol smart card interface. the ev kit can be purchased directly from maxim. for technical support, go to https://support.maxim- ic.com/micro . when start bit is asserted ea bit status character received between 0 and 200 clock cycles when rstx = low 0 no between 200 and 368 clock cycles when rstx = low 1 yes between 368 and 400 clock cycles when rstx = low 0 yes within the first 368 clock cycles after rstx = high 1 yes between 368 and 4000 clock cycles after rstx = 0 yes
DS8007A multiprotocol dual smart card interface 40 ______________________________________________________________________________________ typical operating circuit vbat v50 vcco vcco dvdd c2 10 f c1 0.1 f c6 0.1 f c12 0.1 f r4 10k r2 10k r3 10k c14 0.1 f c11 0.1 f c4 0.22 f c8 0.22 f c7 0.22 f c5 10 f c3 0.1 f avdd vdd vdd rst sdi card socket sam socket int 40 ale 39 ad0 45 ad1 44 ad2 43 ad3 42 rd 36 wr 37 d0 28 d1 29 d2 30 d3 31 d5 33 d6 34 d7 35 cs 38 i/oaux 2 intaux 41 xtal1 47 xtal2 46 vdda 23 cpa1 21 cpa2 26 cpb1 22 cpb2 24 vup 20 c4a 6 c8a 4 clka 8 rsta 10 vcca 9 i/0a 3 presa 5 gnda 7 c4b 14 c8b 12 clkb 16 rstb 18 vccb 17 i/ob 11 presb 13 gndb 15 agnd 25 vdd 27 gnd 19 rstout 1 d4 32 delay 48 u1 cy62148bll-70sxc a17 1 a16 2 a14 3 a12 4 a7 5 a6 6 a5 7 a4 8 a3 9 a2 10 a1 11 a0 12 d0 13 d1 14 d2 15 gnd 16 d3 17 d4 18 d5 19 d6 20 d7 21 a10 23 ce 22 oe 24 a11 25 a9 26 a8 27 a13 28 we 29 a18 30 a15 31 vcc 32 sw1 delay 1 2 3 4 c10 22pf u2 p0.4 1 ce2/a16 2 pe2 3 a9 4 p0.3 5 a8 6 p0.2 7 a13 8 p0.1 9 r/w 10 p0.0 11 12 13 msel 14 p1.0 15 a14 16 p1.1 17 a12 18 p1.2 19 a7 20 p1.3 21 pe3 22 pe4 23 a6 24 p1.4 25 a5 26 p1.5 27 a4 28 p1.6 29 a3 30 p1.7 31 32 a2 33 rst 34 a1 35 p3.0/rxd 36 a0 37 p3.1/txd 38 p3.2/int0 39 p3.3/int1 40 p3.4/t0 41 vrst 42 pf 43 p3.5/ti 44 p3.6 45 p3.7 46 xtal2 47 xtal1 48 p2.0 49 p2.1 50 p2.2 51 gnd 52 sdi 53 v bat v cc v cc0 54 d0 55 p2.3 56 d1 57 p2.4 58 d2 59 p2.5 60 d3 61 ce4 62 ce3/a15 63 p2.6 64 d4 65 p2.7 66 d5 67 nc68 68 d6 69 ale 70 d7 71 ce1n 72 nc73 73 ce1 74 p0.7 75 a10 76 p0.6 77 pe1 78 p0.5 79 a11 80 y1 14.7456mhz c15 22pf c13 22pf y2 14.7456 mhz c9 22pf 12 2 1 3 j2 ccm03-3001lft c7 c7 c1 c1 c2 c2 c3 c3 c5 c5 c6 c6 ju9 j1 ccm01-2065lft c7 c7 c1 c1 c2 c2 c3 c3 c5 c5 c6 c6 s1 s1 s2 s2 c8 c8 c4 c4 prog prog DS8007A u3 ds5002fp
DS8007A multiprotocol dual smart card interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 41 2008 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. emvco approval of the interface module (ifm) contained in this terminal shall mean only that the ifm has been tested in accorda nce and for sufficient conformance with the emv specifications, version 3.1.1, as of the date of testing. emvco approval is not in any way an endorsem ent or warranty regarding the completeness of the approval process or the functionality, quality or performance of any particular product or service. emv co does not warrant any products or services provided by third parties, including, but not limited to, the producer or provider of the ifm and emvco ap proval does not under any circumstances include or imply any product warranties from emvco, including, without limitation, any implied warranties of merc hantability, fitness for pur- pose, or noninfringement, all of which are expressly disclaimed by emvco. all rights and remedies regarding products and servic es which have received emvco approval shall be provided by the party providing such products or services, and not by emvco and emvco accepts no liabil ity whatsoever in connection therewith. package type package code document no. 48 lqfp c48l+1 21-0054 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to th e package regardless of rohs status.

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